Aldec Releases Mixed Language Hardware Acceleration

Contact:        Eric Seabrook
Aldec, Inc.
(702) 990-4400 ext. 224
erics@aldec.com

FOR IMMEDIATE RELEASE


Henderson Nevada, October 26th, 2001 - Aldec, Inc., a leading supplier of HDL design entry and verification tools for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today the support of mixed VHDL, Verilog and EDIF using a patented hardware acceleration methodology. Riviera IPT (Incremental Prototyping Technology (tm)) is the first and only mixed language simulator with built-in hardware acceleration to handle ASIC designs in excess of 10 million gates.

Mixed Language Simulation
Based on Aldec's proven common kernel VHDL, Verilog and EDIF simulator, Riviera IPT can accommodate memories, DSPs, ASICs and other devices, allowing joint verification of legacy designs, EDIF-based IP cores, existing hardware and HDL blocks. Such comprehensive coverage makes Riviera IPT the most universal design verification solution.

"With the ability to accelerate designs utilizing VHDL, Verilog, and EDIF, it creates a very flexible environment for design teams working with different languages and Intellectual Property," stated Eric Seabrook, Riviera Product Marketing Manager for Aldec.

Acceleration Performance
Riviera IPT allows EDA departments to speed up design verification by a ratio of 10 - 100x over traditional RTL simulators. This kind of performance virtually eliminates verification bottlenecks and speeds time-to-market from months to weeks. The Incremental Prototyping Technology(tm) enables the designer to verify and optimize their design in manageable, smaller sized blocks according to project schedules. Each block is verified in software by the Riviera RTL simulator before being "pushed" into hardware. The hardware resident blocks remain "connected" with HDL blocks in the RTL simulator by a patented Riviera approach. Each newly tested HDL block is being "pushed" into hardware. In the end, most design blocks reside in the hardware and verification is performed at ultra high speed. This allows designers to greatly increase the testbench coverage and leads to enhanced design quality without traditional time penalties.


Price And Availability
Riviera IPT is currently available in two configurations; v800, which accommodates 200k ASIC gates and v2000, which accommodates over 500k ASIC gates. v6000 is currently in development and will support designs in excess of 1.5 million ASIC gates. The pricing for Riviera IPT starts at $90,000 or can be leased for less the $10,000 per quarter and is sold directly by Aldec in the U.S. and authorized international distributors. Riviera IPT Beta versions started shipping in July 2001. The deliveries of Riviera IPT will start in October 2001. For additional information about Riviera, go to www.aldec.com.

About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
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Riviera and Incremental Prototyping Technology are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners